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As electronic packages become increasingly complex, designing and building a cost-effective, robust product in a timely manner has become one of the biggest challenges facing packaging specialists. The increased need for higher silicon density drives packaging engineers to use stacked die (SCSP) andstacked package (PoP) configurations. Some of key material challenges related to these packages include: • DDF Die Attach Film thin die stacking processes,
• FOW Die Attach Film for same-size die stacking,
• Spacer Die Attach Paste, an alternative to FOW forreduced cost,
• Molding compounds with targeted performance forthin stacked die packages,
• “Material Sets” in which the above products arecombined to ensure system compatibility, reliability,and ultimately a much lower total cost of ownershipoverall Why stacked die?
Traditional single die integrated circuit (IC) packaging designs are being replaced by more complex, multidie packaging configurations for today’s high demand applications. With the trend towards products offering more functionality and higher performance at a lower cost, package designers have found stacked die CSP (SCSP) packages and the like to provide higher performance while consuming the same HDI footprint as conventional single die packages. SCSPs often integrate an ASIC and memories such as flash, SRAM and DDR into one package by stacking die, interconnecting them with wire bonding and molding all into one JEDEC-standard package. They provide the smallest footprint and lowest profile compared to 3D stacked packages. They also have the lowest packaging cost compared to individually packaged die or other 3D packages. Materials selection
Extensive work has been published on these new package designs, including die layout and wirebond optimization schemes, thin die handling and electrical/RF performance optimization. The packaging materials used in stacked die packages, however, are often ignored. Designing packaging materials that enable the performance and reliability of high density stacked packages requires a systems approach. Each material used in these complex IC packages interact with each other, and the package configuration, to generate interfaces and stresses that contribute to the overall package performance. Furthermore, the material systems are important factors in the cost and manufacturing process complexity of packaged devices. To minimize costs associated with redesign or rework, it is critical to select the right materials system for a package at the design phase. Computer aided design tools used in the package design process often dictate materials selection. However, in many cases, the possible variations in materials performance and process conditions are neglected in the design and simulation process. More importantly, the interactions between packaging materials/components are usually unknown and not considered until the experimental prototyping and assembly process development stages. Often, because of the incompatibility of packaging materials, the package design has to be changed or modified late in the design or production ramp stage. Stacked Die Packaging is packaging technology with 2 or more die stacked in a single package or multiple packages stacked together resulting in: • Smaller, thinner and lighter packages
• Reduced packaging costs and components
• Reduced system level cost for system in package(SiP) vs. system on chip (SoC) approach
• System level size reduction due to smallerfootprints and decreased component count (SiP) Material sets and component interactions
Materials sets are combinations of packaging materials designed to work together synergistically. Rather than selecting and optimizing each single packaging material to be used in a package individually, then bringing each of them together at the end to hope they function well together, materials sets are designed and optimized to be used to together as a set from the design stage. Material interactions, such as interfacial adhesion, cure inhibition and differential stresses are optimized to provide the bestcombination of material properties for a specific package. In the case of a stacked die CSP, the material set consists at a minimum of a first-die die attach material, a second-die (and higher) die attach material and a molding compound. Additionally, in the case of a flip-chip stacked die package, liquid underfill as well as first level flux is incorporated into the package design and must be optimized to work together. As a first step in the material set design, it is important that the chemistry of each of the materials is compatible with each other. For example, a flux residue under the flip-chip of a stacked flip-chip/wirebond package may cause cure inhibition of the underfill material selected. Figure 6 shows the effect of flux residue cure inhibition on the underfill used for a WLCSP application. The flux/underfill interaction causes the underfill to remain uncured after processing, thus creating a severe reliability concern. Simply selecting a flux and underfill independently without understanding the materials’ compatibility often results in this type of reliability issue. However, cure inhibition is easily avoided by designing the underfill and flux chemistry to work together. Likewise, for a stacked die wirebond package, the mold compound and die attach materials must exhibit chemical and mechanical compatibility. The mold compound forms a significant bondline with the film die attach beneath each stacked die in a stair-step or criss-cross stacked die configuration, as shown in figure 7. This interface maybe a source for interfacial stress and delamination, or possibly chemical incompatibility. Again, the materialsengineer must design these materials to function togetherin this application to prevent delamination or cure processinhibition. The material set approach to packaging materialsdevelopment allows teams of engineers to cooperativelydevelop the various materials used in a single package,ensuring chemical and mechanical compatibility. Finally, optimizing materials to work together does not end at the design stage. When material sets are brought together in a new package, design considerations become another factor that determines package cost and performance. Package design considerations including the clearance between components and manufacturing process flows can further influence the package cost and performance. Material set optimization takes into account package designs to reduce materials-related performance problems. As an example, the SiP shown in figure 8 contains a flipchip die and multiple 0402 and 0201 discrete components. The packaging materials used in this application include flip-chip flux, liquid underfill, solder paste and mold compound. The design of this package placed the 0402 components within the dispense fillet range of the liquid underfill, resulting in the underfill effectively encapsulating these passive components. When the package was finally overmolded, a delamination between the mold compound and the passive components was observed (see figure 9). The underfill and mold compound materials were not designed for this application, resulting in significant stresses at the interfaces between the passive components, underfill and mold compound. By working with the packaging engineers, an optimized material set was designed for this package configuration, reducing the interfacial stress incompatibility and thereby meeting the package perforamance requirements. Conclusions
Packaging materials are critical factors in cost, process and performance of high density IC packages. To minimize costs associated with redesign or rework, it is essential to select the right materials for a package at the design phase. Packaging materials are often selected based on simulation results and design specifications. However, in many cases, the possible variations in materials performance and process conditions are neglected in the design and simulation process. More importantly, the interactions between packaging materials/components are usually unknown and not considered until the experimental prototyping and assembly process development stages. In certain cases, because of the incompatibility of packaging materials, the package design has to be changed or modified. Optimized material sets designed to work together to meet specific package requirements can minimize process costs and provide optimized package performance. Michael Todd, PhD, Henkel Corporation Figure 6 Figure 7 Figure 8 Figure 9 Stacked Die Packaging Stacked Die Packaging is packaging technology with 2 or more die stacked in a single package or multiple packages stacked together resulting in: • Smaller, thinner and lighter packages
• Reduced packaging costs and components
• Reduced system level cost for system in package (SiP) vs. system on chip (SoC) approach
• System level size reduction due to smaller footprints and decreased component count (SiP) | Packaging materials for stacked die packages The development and optimization of the packaging materials for stacked die packages is an important first step in developing a packaging materials strategy. Bringing those materials together, however, creates new challenges. Materials suppliers that have the capability to develop materials sets that optimize individual materials performance as well as validate the compatibility of those materials deliver a complete materials solution to the packaging specialist. Emergence of die attach films
All stacked-die packages require wafer thinning. The packages shown in figures 1 and 2 use wafers thinned down to 75μm and 25μm, respectively. Thin wafers left unsupported will bow and curl under the stress of the numerous thin-film layers of the circuit and the thick passivation layer. Wafer thinning in-line supports wafers on tape for better process control and minimum breakage from handling. The same in-line system can attach a thin 20-μm die attach film from a roll to the back of the wafer integrated on the saw tape. This technology, known as “dicing die attach film”, or DDF, enables handling of thinned wafers down to 50-microns in thickness or less. DDF replaces die attach paste in stacked packages for its good control of paste bleed, creeping effect to die edge and consistent bondline control (BLT) at desired thickness. When DDF is used, a wafer is laminated on DDF film, then diced, UV cured (if the dicing tape is a UV tape), and diepicked and attached. During die picking, easy release and clean separation between the die bonding film and dicing film is critical. Die placement speed and pressure will determine the DDF total cost of use. Most importantly, the DDF provides support for handling the thin wafer, thereby allowing ever thinner die to be packaged. Figure 3 illustrates the importance of using a DDF to support a wafer thinning below 100-microns. Recently introduced, flow-over-wire (FOW) materials allow same-size die stacking with a laminated die attach film. The FOW film is combined with the dicing tape, similar to the DDF. When FOW is used, a wafer is laminated on FOW film, then diced, UV cured (if the dicing tape is a UV tape), and die-picked and attached. During die picking, easy release and clean separation between the die bonding film and dicing film is critical. In addition, die placement speed and pressure will determine the FOW total cost of use. The FOW is designed to flow over the wirebonds of the die below the one being placed, eliminating the need for spacer silicon die or the need to stagger sequential die. Overall, a smaller package (thinner and/or smaller footprint) is possible with FOW film processing in stacked die packages. Figure 4 shows the encapsulated wirebond wires of a stacked package built with a FOW film. As you can see from this photo, the FOW film must flow around the wirebonds without causing mechanical distortion. Similar to DDF films, the FOW films should process through wirebonding without cure in order to minimize process steps. Spacer Die Attach Paste is an alternative worth consideration that may provide the same performance advantages as FOW while using the existing paste-dispensing infrastructure without additional capital expenditures. Mold compound optimization
In additional to the innovation in die attach technology, new developments in mold compound materials have also enabled stacked die packages to meet density and performance requirements. The mold-cap thickness of stacked package configurations, for example, must be less than the solder ball standoff height of the stacked top package. For CSPs with 0.5-0.8 mm ball pitch, 0.2-0.4 mm ball standoff height has been adopted in compact applications, necessitating thin molding technologies. Because of the thin mold cap as well as a flexible thincore substrate, warpage can be severe in cases where the thermal mechanical properties of the mold compound are not well balanced with other packaging materials. Warpage is one of the major concerns when manufacturing stacked die and stacked-package IC packages because obtaining and maintaining a reasonably flat package is critical to successful singulation and board level soldering process yields. To address this issue, new mold compounds have been designed specifically for thin stacked die packages to minimize package warpage. By tailoring the coefficient of thermal expansion, modulus, glass transition temperature and cure shrinkage of the mold compound, optimized systems may be designed for specific package designs. As an example, figure 5 illustrates the warpage of a stacked die CSP package as a function of temperature for several mold compounds with different thermal mechanical properties. The data in figure 5 was measured using Moire interferometry analysis of a 2-die stack CSP built on a 0.2mm BT core with 1mm total package thickness. The graph illustrates that the CSP package molded with a traditional BGA mold compound exhibits a negative warpage (smile face) at ambient temperature. However, during reflow processing, the package warpage inverts to become positive (frown face). This package inversion causes high stress on the CSP solder interconnects during package cooling from reflow process temperatures. On the other hand, the CSP packages molded with the two mold compounds designed specifically for thin mold cap POP packages exhibit a negative warpage (smile face) from room temperature throughout the entire reflow process and back to room temperature again. This warpage consistency throughout the reflow process ensures high interconnect yields and reduces package stresses. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 | Acknowledgments The author would like to thank Irving Chien, Hao Tang, Jin-O Choi, Howard Yun, Jack Zhang and the entire Henkel development team for their contributions to the stacked die materials development, FEA analysis and package testing. Additional thanks should be extended to our corporate partners in this development effort. References
1. Dreiza, M. et al, “Stacked Die Package Design Guidelines”, Proc IMAPS Conference, 2004
2. Karnezos, M. et al, “Stacked Die Packaging: Technology Toolbox, Step 8”, Advanced Packaging, 2004.
3. Mathews, D. J. et al, “RF System in Package: Considerations, Technologies and Solutions”
4. Maekawa, Shinichi, “Recent assembly process technology to achieve the 9 stacked MCP,” Proc 12th Annual International KGD Packaging & Test Workshop, Napa, CA, Sept. 2005.
5. Hynix Corporation This white paper was originally presented at the High Density Packaging Conference, Shanghai, China, 2007. The full version can be viewed or downloaded at www.emasiamag.com in the White Paper section. Michael Todd can be reached at Michael.todd@us.henkel.com | |
