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The increasing popularity of high density interconnect (HDI) printed circuit boards, and rising usage of high speed low voltage differential signals (LVDS), uBGA devices (see figure 1) are creating new challenges for test access on today’s printed circuit board (PCB) assemblies. These factors, coupled with continued manufacturing cost pressures, shorter design cycles and demand for high quality products, call for us to take stock of current in-circuit test (ICT) methodologies, and review recent developments and solutions available to help manufacturers address the current and future PCBassemblies limited access challenges. Traditional ICT limited access solutions such as 1149.1 boundary scan testing, analog cluster testing, and digital cluster testing are no longer sufficient to address the increasing complexity of today’s PCB assemblies, which are expected to continue their downward trend in testaccess (see figure 2). With traditional ICT methodologies, the amount of test coverage is limited by the degree of test access allowed by the board’s complexity, as can be seen in the dark blue line in figure 3. To address this widening gap, recent ICT methodologies have evolved to enable manufacturers to continue deploying in-circuit test as part of their manufacturing test strategy (pink trend line). These include new generations of vectorless test, including network parameter measurement, IEEE 1149.6 standard-enabled boundary scan capabilities, as well as the latest powered vectorless test technology just introduced by Agilent Technologies. Let’s take a closer look at how each of these recent ICT methodologies works to recover the loss of test coveragedue to access limitation. • IEEE standard 1149.6 boundary scan
This new ICT solution extends IEEE 1149.1 boundary scan standards to include the new IEEE 1149.6 standard, delivering a limited access solution that enables test coverage extension on short and opens on differential interconnect 1149.6 nodes, as well as coverage on external capacitors on differential 1149.6 nodes. • Bead probe technology
Another solution that addresses limited access challenges on PCB assemblies is the Agilent Medalist bead probe technology, which specifies how test targets, or bead probes, can be placed directly onto copper signal traces, providing test access points virtually anywhere on a board layout, resulting in wider test coverage. This methodology provides electronics manufacturers with excellent in-circuit test access on today’s increasingly dense PCBs as well as designs with high-speed circuits. Bead probe technology can be implemented with no changes to existing surface mount technology (SMT) processes. It also eliminates the need for time consuming re-routing of signal paths during layout to accommodate traditional test pads. Subsequently, products get to market faster when time consuming negotiation between design and test departments is reduced. This method opens up more probing options, thereby simplifying ICT test fixtures. • Network parameter measurement
Proper grounding is becoming increasingly crucial with higher on-board signal speeds, for example on PCIe, DDR and SATA connectors. With increased speeds, opens on ground pins may lead to lowered signal integrity design margins, increased bit-error rates (BER) and increased radiated electromagnetic interference (EMI). Network parameter measurement technology allows users to detect opens on power and ground pins on connectors. Prior to its introduction, many industry players had conceded this area of defects as beyond existing ICT capabilities. • Powered vectorless test
Perhaps one of the most significant breakthroughs in ICT is the introduction of powered vectorless testing. This is a hybrid between two established test methodologies in today’s electronic manufacturing test environment: Boundary scan and vectorless testing. The result is a powerful tool that combines the standardized, limited access, digital stimulus capability of boundary scan with the simplicity of vectorless test. Manufacturers of PCB assemblies now have the option to design circuit boards with less electrical test access, thus reducing test resources. Also, fewer probes in the test fixtures mean reduced strain on the PCB assemblies, thereby further preserving the integrity of the board. With powered vectorless testing, it is expected that the test coverage lost on traditional ICT method will be recovered to meet the expected test coverage of today’s complex PCB assemblies. Jun Balangue, Agilent Technologies Figure 1 Figure 2 Figure 3 Table 1 About the author:
Jun Balangue is the Technical Marketing Engineer at Agilent Technologies. He can be reached at Jun_balangue@agilent.com. | 
