Sanmina-SCI Announces New Technology for Chip Substrates and High-Performance PCBs
8 April 2008
Sanmina-SCI Corporation has announced SuperBC--a new patent pending technology for Buried Capacitance applications in providing bypass capacitance inside silicon chip packages and high-performance PCBs--at Apex 2008 in Las Vegas, USA. This also includes a layer of Sanmina-SCI’s patent pending eESD embedded electrostatic discharge (ESD) protection technology which, if designed properly, can protect 100 percent of the I/O pins on a chip or PCB from voltage transients as high as 30K volts.
Sanmina-SCI’s PCB Division plans to collaborate with their joint development partner Shocking Technologies and BC Licensee Oak-Mitsui to integrate Xstatic voltage switchable dielectric (VSD) material with ultra-thin layers of nanopowder loaded Faradflex material.
“SuperBC laminate will provide next-generation levels of capacitance density along with other enabling performance characteristics,” stated George Dudnikov, Senior Vice President and Chief Technology Officer for Sanmina-SCI’s PCB and Backplane Divisions. “The technology uses a base 1 or 2 mil BC core onto which additional 8 micron or thinner high Dk dielectric layers are added to form a composite capacitance core. Multiple dielectrics can be added to either boost bulk planar capacitance values or segregate the Power Distribution System (PDS) by different voltage levels or noise budgets. To date, we are producing SuperBC cores with 45 nanofarads per square inch of capacitance in an overall thickness of less than 6 mils. The result is 90 times the capacitance density of ZBC2000, the industry market-leading capacitance material, in a thinner construction than a standard 4 mil dielectric power ground layer,” continued Dudnikov.
SuperBC can also include a layer of eESD which uses a thin continuous layer of Shocking Technologies Xstatic VSD material under a ground plane inside the PCB. The VSD material is programmed to switch from being a pure dielectric insulator to pure electrical conductor, dissipate the ESD transient to ground, and then reset itself – all in less than a nanosecond. Testing has shown that protection levels up to 30K volts are achievable.
“As processor frequencies and bandwidth requirements continue to increase, PDS designers are looking for more and more low inductance capacitance for bypass,” added Dudnikov. SuperBC can be utilized in high-performance server and telecom applications where it can significantly reduce, if not totally eliminate, the need for surface bypass or specialty capacitors. It will also be very enabling as a core for chip packaging substrates where higher levels of distributed capacitance can be placed very close to the silicon chip. With the addition of a layer of eESD, critical electrostatic discharge protection can be added to improve reliability of the electronic system.”
