Inspection

When selecting an automatic optical inspection (AOI) system, test circuit boards can be prepared such that all typical production errors are present.

Error recognition and its reproducibility are key determinants for the quality of an inspection system and inspection programs, the most important factor here being reliable recognition of true errors. These are clear errors, according to IPC-A-610, requiring correction after soldering, which are often associated with additional costs and considerable time delays for rework.

Cycling time and false call rate are also significant factors in the inspection process. Each of these factors (including error recognition) has a direct effect on the other (See illustration 1).

Generally, the recognition of a large number of different errors and slight deviations from the standard, as defined in IPC Standards Class 3, requires a very long inspection depth.

This, for its part, has an effect on the cycling time: The number of errors or deviations that require detection, the longer the cycling time usually required and the higher the probability that AOI will indicate errors that are not true errors, or so-called “false calls”. Naturally the opposite applies for "easy" inspection with a wide tolerance range where the pseudoerror rate is kept low.

Primary objective:
True error detection

The primary objective of AOI evaluation should always be to find all (previously defined) true errors.

Cycling time and false call rate should only be compared in the next step.



Here it is necessary to consider that even an initially high false call rate, for example in a zero-error escape process, can be optimized considerably by offline optimization, use of SPC and other measures, to obtain very good process results in the final analysis.

While careful preparation for AOI evaluation is essential in determining whether a system satisfies all specified requirements, one should also take future developments into account.

This is so that the inspection process does not reach its limits when converting to a new product. For this purpose the test circuit boards should be provided with a sufficient number of true errors – at least 100 true errors can be used as a guideline.

Particularly, critical errors such as lifted leads or tombstoning should be taken into consideration, because it is very difficult to detect them at a later stage of the process. For this reason, inspection concepts such as the use of component libraries, for example, should be incorporated into
the basic decisions on AOI evaluation.



Error simulation for AOI inspection

Typical types of true errors are illustrated below and the best possibilities for simulation are discussed. The explanations are based on the reflow process, because the greatest process variations are expected here and the soldering process is highly responsible for the optical distinctness of the circuit board, component and solder joint. Nevertheless, some examples can be applied directly to paste printing and the prereflow process.



It is important to ensure that simulation covers the entire bandwidth of the component range. Errors on non-critical 1206 to 0402 versions, or SOICs/PLCCs should also be considered, as should installation of fine pitch components such as TSOPs or QFPs. Plugs, actuators or other special types of components used should be included in the evaluation.


Reproducibility tests

Reproducibility can be achieved as follows: A circuit board with critical errors is inspected repeatedly - 10 to 50 runs – and the results compared and differences verified. Reproducibility of false calls does not represent a clear criterion, because the causes for false calls are frequently toggling of the inspection results around a classification threshold. However, true errors should always be recognized reliably.


Simulation of component errors through manipulation:
• Displaced or twisted components
Components, that are pushed away before soldering (Figure 1, Figure 2), change their position during the soldering process. To prevent this, application of adhesive between the pads after installation and repo-sitioning of displaced components is recommended. The adhesive should not be applied too thick, otherwise normal component drop would obstruct reflow soldering. This correction allows any desired offset limits to be simulated in conformance with IPC610 Class 1-3.

• Missing components
The complete test is accomplished with an empty, soldered circuit board; printed with paste, but without components installed. Missing components can also be simulated by simply removing them from the circuit board (Figure 3).

• Component not soldered due to absence of paste
When the paste is missing or a components not soldered (Figure 4), it is important to observe the alloy used for the substrate. With HAL circuit boards, preliminary tinning is often sufficient to achieve satisfactory soldering results.

Complete absence of paste on eutectric, NiAu or chemical tin circuit boards leads directly to this type of error. It is frequently not simulated sufficiently, because the paste is removed from the pad after installing the components. For this reason simulation of this error should always be accomplished during the paste process. This is most successful when some of the pads on the template are masked from the bottom, whereby it is necessary to ensure that the edges of the cellophane tape are cut smoothly.

As an alternative procedure, individual pads can be cleaned completely with a cotton swab after paste printing.

Here it is necessary to note that it is not sufficient to simply remove the paste in front of the part after installing the components. Practical experience from paste printing has shown that as a rule, 50 percent printing is sufficient for an acceptable solder joint.

With the aid of reduced paste application it is possible to simulate a lean solder joint. The results should be checked afterward (Figure 5).



A further possibility for simulation is to install components on an empty, unprinted circuit board, and then solder them. The components should be attached previously with superglue, wave soldering glue or a transparent adhesive foil to keep them from falling off after soldering. It is simpler to run an empty, unprinted circuit board through the soldering process.

In the wave soldering process errors can be simulated by applying a transparent cream containing silicon to individual pads so that the tin cannot come into contact with the pads.


• Lifted leads
Lifted leads are the most critical errors because they are frequently not recognized during ICTinspection when the component is still in contact with the pad. This error occurs as a result of incorrectly stored or aged parts or other wetting problems. Simulation depends on the type of component in each case. Here are a few examples:


1. Chips
Using a chip with lifted leads as an example, a transparent cream containing silicon is applied to a cap and the component is then positioned between the pads with a high offset and secured with adhesive, if required (Figure 6).

2. ICs, QFPs, PLCCs:
With these components, it is possible to press in a corner pin before soldering so that all other pins stick up at an angle and the cut-off edge of the pins can be recognized exactly. With bar material, individual pins can be bent or lifted before installation. Another variation is to place a chip resistor below a QFP to be assembled. This variation is used frequently in practice and is particularly good for separating chip shooters and fine-placers (Figure 7).



• Component with polarity reversed Components installed with the polarity reversed (Figure 8) can be simulated by repositioning the part backward after installation. Simu-lation can also be accomplished with the aid of the software. For this purpose it is necessary to temporarily reverse the position of the components according to the installation plan.

Simulation of soldering errors:
• Fat solder joints
Additional paste can be applied with a pipette before soldering to simulate a fat solder joint (Figure 9).

• Short circuit

A short circuit can also be simulated in this manner. For this purpose additional paste is applied between the pads (Figure 10). The size of the short circuit can be controlled by the quantity of paste. With wave soldering, current speci-mens from production should be used.

• Tombstones
Simulation of tombstones (Figure 11), also called the Manhattan effect, differs from lifted leads on chips. In this case the components stick up at an angle of 10° to 90°. These typical soldering errors can be simulated by positioning the chips with high offset, so that they make contact with the pad only in the soldering direction.

Varying melting points and different capillary effects can cause the components to stick up. Here, the component should not be set in the offset position with adhesive.

Simulation of component errors Typical component errors such as face down or components turned 90° can be simulated after installing the components, but before soldering, bysimply turning them manually (Figure 12), (Figure 13). Whether face down resistors are recognized as errors depends on the IPC 610 class. In class 3 this is evaluated as an error.









Conclusion
As the descriptions above show, true errors can be simulated or manipulated on circuit boards very simply and quickly. The advantage of such preparation is obvious: Onlyclearly defined error logs allow for theevaluation of inspection quality. Simultaneously the differences between various types of AOI become clear and potential users can be certain of their decisions by comparing and evalua-ting performance. This allows for classification according to a price/ benefit ratio, ensuring the best possible solution for the specific application.

Further information as well as the guidelines 'AOI Evaluation Made Simple' can be obtained by emailing angs@viscom.de.